The invention relates generally to multilevel power conversion devices and more particularly to series resonant converters (SRCs) with clamped capacitor voltage and zero voltage switching (ZVS).
High voltage power conversion systems have many applications, including but not limited to military systems, transportation systems, manufacturing, electric power utilities, distributed power generation, electric power distribution, high voltage (HV) direct current (DC) transmission systems, and many other applications and industries familiar to those of skill in the art. Various methods can be used to attain a power conversion system having a high output voltage. One method is to use a multilevel power converter arrangement. The desired output voltage of the power conversion system is one factor that determines the number of levels a multilevel power converter might have, another factor is the type of switching devices the power converter uses, and still another factor is the category of converter used.
As is known in the art, multilevel converters belong to three broad categories: Diode-clamped converters; capacitor-clamped (flying capacitor) converters; and cascaded converters. Cascaded converters may be divided into converters with separate voltage sources (see, e.g., U.S. Pat. No. 6,005,788 to Lipo et al, U.S. Pat. No. 5,638,263 to Opal et al., and U.S. Pat. No. 5,625,545 to Hammond), and converters without separate voltage sources.
One problem associated with diode-clamped converters is voltage imbalance between series-connected DC bus capacitors and complicated control required for capacitors balancing. Another negative aspect of these converters is the unequal conduction time of switches. Diode-clamped converters also need clamping diodes with blocking voltage that increases with the number of levels. As the number of levels increases (e.g., beyond five levels), the diode-clamped converter topology can become unwieldy and difficult to realize.
Capacitor-clamped topologies rely on capacitors connected across transistors to limit their off-state voltage. Similarly to diode-clamped topologies, the capacitor voltages have to be regulated using complex switching algorithms for power semiconductors. Another disadvantage is that the flying capacitor converters require a significant number of large capacitors with voltage rating that increases with the number of levels. As with the diode-clamped converters, capacitor clamped inverters can be awkward and difficult to achieve beyond five levels.
Cascaded topologies use series connection of individual cell converters and do not need clamping diodes or capacitors. Converters with separate DC sources ensure inherent voltage balance across individual cells. However, since these converters require multiple, isolated DC sources (for example, via a separate line frequency transformer rated for full load power), their use is somewhat limited.
Cascaded converters without separate voltage sources (see e.g., T. A. Lipo et al, “Hybrid Topology for Multilevel Power Conversion”, U.S. Pat. No. 6,005,788, Dec. 21, 1999) use a DC supply for one converter cell while the remaining sources are substituted by capacitors. Thus, the cell fed by the power supply processes the full load power while other cells improve the output voltage quality. This topology has different voltage levels across individual cells and needs to simultaneously control both capacitor voltages and the switching algorithm that forms the output voltage.
A modular, multilevel converter with a single power source that does not feature equal power distribution between individual cells is described in U.S. Pat. No. 6,236,580 to Aiello et al. Although this topology has a three-phase power source, it relies on single-phase power processing that leads to oversized DC filter capacitors inside cells. Also, because cell converters comprising this topology are connected in series on both sides of the isolation boundary, this approach does not guarantee equal power distribution between cells.
In general, known converters do not adequately address operation of fast semiconductors in high voltage (HV) switching environments that may generate a spurious turn-on. This effect results from the combination of HV and high frequency (HF) that subjects transistors in a bridge circuit to high dV/dt. The rapid voltage change produces large parasitic currents internal to semiconductors during hard switching events such as reverse recovery of the MOSFET body diode and turn-on of one transistor in a bridge leg. These transients might cause simultaneous conduction of transistors connected across the input bus (cross-conduction) resulting in failures of HV, HF converters, as shown in the prior art configuration of FIG. 1.
FIG. 2 illustrates, for a prior art converter a cross-conduction observed in hard-switching converters at a low input voltage of 270 VDC that will be more pronounced in high voltage converters. Active pull-down gate drive circuits and reduced internal gate resistance can alleviate this problem, but they do not address its root cause.
A power converter comprising two power cells with inherent power balance between the individual cells is disclosed into the aforementioned U.S. Pat. No. 6,873,138, which has been incorporated herein by reference. In addition to equal power sharing between the individual cells, the power converter of the '138 patent utilizes zero voltage switching (ZVS), which makes it well-suited for high voltage, high frequency switching environments. The two power cells in this converter are connected in parallel via a compensation circuit to form a dual clamped-mode series resonant converter (SRC). In such a converter, ZVS can be obtained for a full range of output load conditions and results in robust, reliable operation. However, parallel connection of the power cells is a limiting factor in high voltage applications.